The present invention concerns a high density, high speed semiconductor memory suitable to application in a case of constituting a semiconductor memory device, particularly, a large scaled integrated circuit.
Heretofore, DRAMs (Dynamic Random Access Memories) have been often used in view of their large capacity as general purpose large capacity memory devices (large capacity memories). However, in DRAM, since it is necessary to store information in the capacitor in the memory cell and detect and amplify minute signals formed from the stored charges, the operation tends to be unstable. In order to prevent erroneous operation caused by various noises formed in the memory chip and noises intruding from natural world such as noises or xcex1-rays, it is necessary to ensure the amount of signal to a predetermined value or more and this imposes a limit for the reduction of the capacitance of the capacitor. Accordingly, a high density, can not be attained by merely reducing the size of the existent memory cell. Accordingly, developments for memory cells capable of storing information with a smaller amount of charges have been conducted vigorously.
As an example, there is a PLED (Planer Localized Electron Devices) memory cell as described in 1997 xe2x80x9cInternational Electron Devices Meeting Technical Digestxe2x80x9d in the proceedings of American Academic Conference, Session 7.7.1, pp. 179-182.
The PLED memory cell has a feature in providing a floating gate and a vertical transistor laminated on a memory cell, in which information is stored in the floating gate and control is conducted by the vertical transistor. With such a structure, a gain cell structure having a signal amplifying effect in the cell itself is formed and information can be kept with a small amount of charges and, in addition, a small cell size is attained irrespective of the two transistor system. However, it is necessary to dispose a tunneling multi-layer with a large number of lamination on the floating gate and it involves a problem of requiring many process steps and increasing the cost for the production.
On the other hand, another category for a general purpose high density memory device is a non-volatile memory device and an example thereof is an MNOS (Metal-Nitride-Oxide-Semiconductor) type EEPROM (Electrically Erasable Programmable Read Only Memory). Since the memory device of this type has a non-volatility and, at the same time, a gain structure is formed, it can keep the information with a small amount of charges. However, it requires a high voltage for writing the information into the memory cell, and the writing time is as slow as about 1 ms, so that it can not be used as a high speed memory device. In addition, the rewriting cycles are restricted by degradation of the dielectric film to about 105 to 106 cycles.
In an MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure improved for the MNOS type (refer, for example, to xe2x80x9cIEEE Transaction on Electron Devicesxe2x80x9d, US Magazine, (November 1993) , vol. 40, No. 11, pp. 2011 to 2017, fatigue of 107 cycles is attained. However, the MONOS type EEPROM has a two transistors per one cell constitution in order to provide a random access function, so that the cell size is large and it is difficult to attain a higher density memory device than usual.
An object of the invention is to solve the foregoing problems in the prior art and provide a small-sized highly reliable, high density, non-volatile semiconductor memory device having excellent fatigue and having a random access function.
The MNOS type memory device described above has a silicon oxide layer and a silicon nitride layer formed on the layer for storing information. An information storing portion is a storage node formed in a silicon nitride layer or at a boundary where both layers are in contact with each other and injection and discharge of carriers into and out of the storage node are conducted exclusively from the channel to the silicon oxide layer of the memory cell transistor. Accordingly, the fatigue is determined by the durability of the silicon oxide layer. However, the silicon oxide layer has a nature of being liable to be deteriorated by the application of a high electric field along with injection and discharge of the carriers and the memory durability is determined thereby. The silicon oxide layer is disposed in contact with the channel, because the silicoin oxide layer has a high barrier height required in the storage operation.
On the contrary, the silicon nitride layer has a property more excellent in the durability than the silicon oxide layer. However, the MNOS type memory has a structure not utilizing the characteristics of the silicon nitride layer.
On the other hand, in the PLED type memory device as described above, carriers are injected and discharged into and out of the floating gate from the tunneling multi-layer and control for writing and erasure is conducted by the control gate of the vertical transistor formed above the memory cell transistor. That is, the PLED type adopts not to inject and discharge of carriers upwardly on the side of the channel of the memory cell transistor but injection and discharge of the carriers in the downward direction from the layer thereabove.
When injection and discharge of the carriers from above is applied to the MNOS type, the silicon nitride layer can be utilized instead of the silicon oxide layer as the intermediate layer for charging and discharge of the carriers. In addition, since the vertical transistor required for this purpose has a structure stacked on the memory cell transistor as described above, the cell size increases only slightly. Further, since it has a transistor for control, it can provide a random access function.
This invention has been achieved based on the novel concept of applying injection and discharge of the carriers from above to the MNOS type having non-volatility. That is, in order to attain the foregoing object, the semiconductor memory device according to this invention has a feature in forming two kinds of dielectric films on the channel of a MOS (Metal Oxide Semiconductor) and laminating another vertical MOS transistor using the control gate of the above-mentioned transistor as a substrate to a portion thereabove.